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Description |
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16-Bit Carry-Select Adder
(3 pages, updated 9/99)
A carry-select adder implemented in the AT6000 achieves speeds 40% faster by performing additions in parallel and reducing the maximum carry path. |
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16-Bit Up/Down Counter Shift Register
(4 pages, updated 9/99)
The AT6000 Series FPGA lets the designer implement a synchronous, 16-bit Up/Down Counter/Shift Register that operates at 22 MHz under the worst commercial operating conditions. |
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16-Bit, Four-To-One Multiplexer with 15-ns Delay
(3 pages, updated 9/99)
The AT6000 Series FPGA lets the designer implement a 16-bit four-to-one multiplexer with a 15 ns delay from the select control to the most significant output bit. |
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16-Word by 8-Bit FIFO
(5 pages, updated 9/99)
The AT6000 Series FPGA lets the designer implement a synchronous, first-in, first-out (FIFO) register buffer with a word width and depth tailored to specific design needs. |
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24-Bit Magnitude Comparator with 50-ns Response
(5 pages, updated 9/99)
The AT6000 Series FPGA lets the designer implement a magnitude camparator that can compare two 24-bit binary integers in 50 ns. |
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3x3 Convolver with Run-time Reconfigurable Vector Multiplier in Atmel AT6000 FPGAs
(9 pages, updated 8/99)
In this Application Note we present an efficient single-chip FPGA implementation of a bit-parallel 3x3 symmetric convolver that features run-time software-configurable convolver coefficients (taps). |
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8-Bit S-P/P-S Corner-Bender Data Converter
(5 pages, updated 9/99)
Using the AT6005 device, two S-P/P-S corner-bender circuits were implemented: one optimized for area and power consumption, the other for speed and expandability. |
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9-Bit Programmable Terminal Counter
(5 pages, updated 9/99)
The AT6000 Series FPGA lets the designer implement a synchronous, programmable 9-bit terminal counters optimized for speed or layout area. |
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AT40K Check Function on Configuration
(7 pages, updated 4/01)
The AT40K and AT40KAL family supports a check function in mode 2 configuration SRAM data (a write Verify). |
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AT40K Series Configuration
(41 pages, updated 3/02)
Configuration is the process by which a design is loaded into an AT40K/AT40KAL series FPGA. AT40K/AT40KAL series devices are SRAM based and can be configured any number of times. |
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AT6000 Series Configuration
(21 pages, updated 9/99)
This document suggests guidelines for device congifuration and describes each of the configuration modes in detail. |
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Barrel Shifter
(3 pages, updated 9/99)
The AT6000 Series FPGA allows the designer to implement fast compact 8-bit barrel shifters, and modular shifters that can be easily sized for specific needs. |
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Compact, Loadable 16- and 32-Bit Binary Counters
(4 pages, updated 9/99)
The AT6000 Series architecture accommodates dense, synchronous, loadable binary counters. |
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Configuration Compression Algorithm
(2 pages, updated 9/99)
The AT6000 Series FPGAs are SRAM-based and can be reconfigured to perform different applications in a system. |
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Conversion from Xilinx to Atmel FPGAs
(8 pages, updated 7/00)
Atmel's IDS software can convert XNF designs. |
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Data Acquisition Systems Using Cache Logic FPGAs
(5 pages, updated 9/99)
This Application Note describes our enabling technology to make adaptive hardware possible for Data Acquisition, Logic Analyzer, and other instrumentation products. |
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Digital Frequency/Phase Comparator (DFPC)
(4 pages, updated 9/99)
The AT6000 Series FPGA lets the designer implement a digital frequency/phase comparator (DFPC) that interfaces to a voltage controller oscillator (VCO). |
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DSP Acceleration Using Reconfigurable Coprocessor FPGA
(6 pages, updated 9/99)
Digital signal processors (DSPs), like their FPGA counterparts, are proliferating into a broad range of compute intensive applications, including telecommunications, networking, instrumentation and computers. |
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Edge Detection in AT6000 FPGAs
(5 pages, updated 9/97)
In the Application Note we present a reference design of a fully pipelined bit-parallel edge detection circuit that utilizes only pipelined adders and fits into one AT6010 FPGA. |
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FPGA-based FIR Filter Using Bit-Serial Digital Signal Processing
(10 pages, updated 9/99)
This Application Note describes the implementation of an FIR Filter with variable coefficients that fits in a singel AT6002 FPGA. |
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FPSLIC Prototype Kit: Using ATDH40M with Both AT94K and AT40K Devices
(2 pages, updated 7/01)
You can modify the existing ATDH40M Prototype system to work with FPSLIC and the existing AT40K device. |
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High-Speed, Loadable 16-Bit Binary Counter
(5 pages, updated 9/99)
The AT6000 Series FPGA lets the designer implement a fast synchronous, loadable 16-bit binary counter that operates at 70 MHz on and off chip under the worst commercial operating conditions. |
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IEEE 1149.1-1990 Standard Test Access Port & Boundry-Scan
(8 pages, updated 9/99)
For system or board diagnostics, AT6000 Series devices can be programmed with the 1149.1 standard test logic and then reprogrammed for normal operation when the diagnostics are complete. |
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Implementing a Single-coefficient Multiplier
(5 pages, updated 03/02) |
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Implementing Bit-Serial Digital Filters
(9 pages, updated 9/97)
This Application Note describes the implementation of digital filters in the Atmel AT6000 Series FPGAs. |
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Implementing Cache Logic with FPGAs
(5 pages, updated 9/99)
This Application Note describes our enabling technology to make adaptive hardware possible for electronics systems. |
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IP Core Generator
(5 pages, updated 2/02)
Parameterized IP Core Generator available for the AT40K/AT40KAL series FPGA and AT94K series FPSLIC. |
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IP Core Generator Absolute Value
(3 pages, updated 1/02)
This generator takes an input and generates the absolute value. |
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IP Core Generator Accumulator
(4 pages, updated 1/02)
The Accumulator generators add a given number to the register initial value. |
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IP Core Generator Adders
(6 pages, updated 1/02)
This generator can be used to generate an n-bit Carry Select Adder. |
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IP Core Generator Bus Ripper
(3 pages, updated 1/02)
The Bus Ripper generator allows the user to produce variable-width “soft” buffers for re-naming buses within a design. |
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IP Core Generator Comparator
(4 pages, updated 1/02)
The Comparator Generator created the follwing comparators: Equals, NotEquals, LessThan, LessThanOrEqualTo, GreaterThan and GreaterThanOrEqualTo. |
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IP Core Generator Constant
(3 pages, updated 1/02)
This generator creates a Constant with the specified values. |
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IP Core Generator Decoder
(5 pages, updated 1/02)
The Decoder generator can be used to create a full or partial decode of the specified number of bits of input or output. |
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IP Core Generator I/O Buffer
(8 pages, updated 1/02)
The bi-directional I/O buffer generator can be used to generate a soft macro (schematic only) which uses the specified options. |
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IP Core Generator Multiplier
(12 pages, updated 12/01)
The Multiplier generator can be used to create a signed or unsigned serial by parallel multiplier with serial output. |
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IP Core Generator Shift Register
(5 pages, updated 12/01)
The Shift-register generator can be used to create serial, serial-parallel, parallel-serial and parallel-parallel shift registers. |
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IP Core Macro Generator Counter
(15 pages, updated 1/02)
Generators used to generate Johnson, LFSR, Prescaled, Ripple Carry or Terminal Counters |
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IP Core Macro Generator Deductor
(4 pages, updated 1/02)
The Deductor generator subtracts a given number from the register initial value. |
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IP Core Macro Generator FIFO
(4 pages, updated 1/02)
This generator creates a First-In First-Out (FIFO) buffer that makes use of the RAM cells in the AT40K Series architecture to produce a compact implementation with no read or write latency. |
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IP Core Macro Generator Flip-Flop
(8 pages, updated 1/02)
The D Flip-Flop generator can be used to create a register bank consisting of D-type flip-flops. |
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IP Core Macro Generator Gray Code
(3 pages, updated 1/02)
The Gray Code generator can be used to convert binary code to gray code or gray code to binary code respectively. |
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IP Core Macro Generator Incrementor/Decrementor
(8 pages, updated 1/02)
The Incrementor/Decrementor by 1 generator can be used to add/subtract 1 to/from the current registered value. This generator can be used to create a macro which increments or decrements by 1 a preloaded value or the data input on each rising (or falling) edge of the clock. |
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IP Core Macro Generator Logic Gates
(4 pages, updated 1/02)
A variety of Logic Gates can be generated, each with a programmable number of inverted inputs. |
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IP Core Macro Generator Look-Up Table
(5 pages, updated 1/02)
The Look-Up Table (LUT), or Generic Cell generator can be used as a convenient interface for generating components using the FGENxx and MGENxx generic cell components in the AT40K macro library. The generator allows complete control over
the function of an AT40K core cell, and it allows this function to be replicated n times. |
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IP Core Macro Generator MUX
(4 pages, updated 12/01)
The Mux generator can be used to generate one or more muxes controlled by a single SELECT bus input. |
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IP Core Macro Generator Negate Function
(3 pages, updated 12/01)
The Negate Function generator can be used to create a two’s complement function implemented in a ripple carry manner. |
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IP Core Macro Generator Pulse Generator
(5 pages, updated 12/01)
This can be used to create a pulse generator that asserts its output once every n clock cycles, where n is a fixed value specified by the user. |
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IP Core Macro Generator ROM
(4 pages, updated 12/01)
The ROM generator is used to create synchronous read-only data memories. The data is generated by reading a user-supplied data file and then using the look-up tables within each core cell to store the data. |
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IP Core Macro Generator Subtractor
(6 pages, updated 12/01)
This generator can be used to create an n bit carry-select subtractor. |
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IP Core Macro Generator Transparent Latch
(4 pages, updated 1/02)
The Latch generator can be used to create a D-type transparent latch. |
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Macro Library
(10 pages, updated 12/01)
The Programmable System Level Integrated (PSLI) library of components can be divided into 2 types of macros: functional and dynamic. Functional macros are compo-nents with fixed functionality, such as the 2-input AND gate. Dynamic macros are designed to allow user specification of any desired functionality attached as an attribute, via an equation string, on the symbol. |
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Modeling Device Power Consumption
(3 pages, updated 9/99)
This Application Note provides a simple method for modeling the active and static power consumption of a AT6005 design. |
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Pulse Width Modulation
(9 pages, updated 9/01)
Pulse Width Modulation is a technique to provide a logic "1" and a logic "0" for a period of time. |
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Recommended Design Methods
(9 pages, updated 9/99)
Described here are a series of guidelines for designing with AT6000 Series FPGAs. |
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Replacement of a RAM with Atmel FreeRAM in Verilog-based Designs
(9 pages, updated 8/01)
Atmel's AT40K/AT40KAL and the AT94K FPSLIC include distributed blocks of RAM throughout the device. These blocks are called FreeRAM. |
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Ripple-Carry Adders
(3 pages, updated 9/99)
With a NAND and an XOR available simultaneously in a single cell, the AT6000 architecture is ideally suited for implementing arithmetic operations, including parallel adders. |
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Second-Order IIR Digital Filter Macro (IIR)
(3 pages, updated 9/97)
This Application Note details implementation of a second-order IIR Digital Filter Macro in the AT6000 Series FPGAs. |
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Standard 8-Tap FIR Filter Macro (FIR8)
(3 pages, updated 9/97)
This Application Note details implementation of a standard 8-Tap FIR Filter Macro in the AT6000 Series FPGAs. |
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Symmetrical 16-tap FIR Filter Macro (FIR16S)
(2 pages, updated 8/97)
This Application Note details implementation of a 16-Tap FIR Filter Macro in the AT6000 Series FPGAs. |
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Symmetrical 24-tap FIR Filter Macro (FIR24S)
(2 pages, updated 8/97)
This Application Note details implementation of a 24-Tap FIR Filter Macro in the AT6000 Series FPGAs. |
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Symmetrical 32-tap FIR Filter Macro (FIR32S)
(2 pages, updated 8/97)
This Application Note details implementation of a 32-Tap FIR Filter Macro in the AT6000 Series FPGAs. |
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Symmetrical 8-tap FIR Filter Macro (FIR8S)
(3 pages, updated 8/97)
This Application Note details implementation of a 8-Tap FIR Filter Macro in the AT6000 Series FPGAs. |
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| Application Example and Algorithms |
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Software |
Description |
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AT40K FPGA IP Core -- AT40K-FFT
(9 pages, revision B, updated 12/08)
Fast Fourier Transform Intellectual Property Core for AT40K FPGAs |
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