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16-bit Arithmetic
(3 pages, updated 4/01)
This Application Note lists program examples for arithmetic operation on 16-bit values. |
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2-Wire Serial Macros
(4 pages, updated 4/01)
The 2-wire serial macros provide a simple method for setting the 2-wire serial features on the AT94K device. |
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Accessing 16-bit I/O Registers
(4 pages, updated 11/00)
This Application Note explains how to access the 16-bit I/O registers from the FPSLIC-AVR Core using the in and out instructions. |
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Accessing the Dual-port SRAM Block from the FPGA Side of the FPSLIC®
(5 pages, updated 7/05)
This application note provides sesigners with an understanding of how to access and achieve optimal performance from the Shared Dual-port SRAM block from the FPGA side of the FPSLIC. |
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AT94K Series Configuration
(38 pages, updated 8/01)
Configuration is the process by which a design is loaded into an AT94K FPSLIC device. AT94K Series devices are SRAM based and can be configured any number of times. |
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AT94K, FPSLIC Interrupt Macros
(6 pages, updated 4/01)
Interrupt macros provide customers with a simple method for enabling/disabling interrupts. |
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AT94K, FPSLIC System Macros
(3 pages, updated 4/01)
The system macros provide customers with a simple method for using system level features on the AT94K device. |
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AT94K, FPSLIC Timer Macros
(6 pages, updated 4/01)
The timer macros provide a simple method for using the timers of the FPSLIC device. |
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AT94K, FPSLIC UART Macros
(3 pages, updated 4/01)
The UART macros provide a simple method for enabling/disabling and configuring the UARTs. |
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AVR-FPGA Interface Design 1
(4 pages, updated 3/03)
Atmel's AT94X sample designs are provided to familiarize with the AT94K FPSLIC Device. This design is intended to demonstrate the communication between the AVR and FPGA utilizing the data bus, interrupts and I/O select signal. |
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AVR-FPGA Interface Design 2
(4 pages, updated 3/03)
Atmel's AT94X sample designs are provided to familiarize with the AT94K FPSLIC Device. This design is an enhancement of the previous design. The only difference between the two designs is this design also stores the interrupt count in the shared dual-port SRAM. |
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AVR-FPGA Interface Design 3
(5 pages, updated 3/03)
Atmel's AT94X sample designs are provided to familiarize with the AT94K FPSLIC Device. This design is an enhancement of the previous design. The only difference between the two designs is this design implements a second counter, which is loaded from the shared dual-port SRAM. |
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AVR-FPGA Interface Design 4
(5 pages, updated 3/03)
Atmel's AT94X sample designs are provided to familiarize with the AT94K FPSLIC Device. This design is an enhancement of the previous design. The only difference between the two designs is this design multiplies the interrupt count of the two counters together, and stores the result in the shared dual-port SRAM. |
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AVR-FPGA Interface Design 5
(5 pages, updated 3/03)
Atmel's AT94X sample designs are provided to familiarize with the AT94K FPSLIC Device. This design is an enhancement of the previous design. The only difference between the two designs is this design transmits/receives the multiplication result from the UARTs. |
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AVR-FPGA Interface Design 6
(5 pages, updated 3/03)
Atmel's AT94X sample designs are provided to familiarize with the AT94K FPSLIC Device. This design is an enhancement of the previous design. The only difference between the two designs is this design also displays the interrupt counts on the AVR general purpose I/Os (PORTD). |
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C Code for Interfacing the FPSLIC AVR Core to AT17 Series Configuration Memories
(17 pages, updated 4/01)
This Application Note describes how to In-System Program (ISP) an Atmel AT17 Series Configuration Memory using the AVR Core of one FPSLIC device and how to use the built-in two-wire serial interface. |
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Divide Routines
(13 pages, updated 11/01)
This Application Note lists subroutines for division of 8- and 16-bit signed and unsigned numbers. |
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DTMF Generator
(9 pages, updated 5/02)
This Application Note describes how the Dual-Tone Multiple Frequencies (DTMF) signaling can be implemented using the embedded microcontroller with PWM and SRAM. |
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Efficient C Coding for FPSLIC Using IAR
(11 pages, updated 11/00)
This Application Note describes how to utilize the advantages of the FPSLIC architecture and the development tools to achieve more efficient C code than for any other Microcontroller. |
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Expanding the FPSLIC I/O Area
(5 pages, updated 3/02)
This Application Note describes how to expand the number of I/O counts using a linked enable signal. |
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Extending FPSLIC Program Code Space to 128 Kbytes by Using External Flash Memory
(9 pages, revision A, updated 6/05)
This design demonstrates how the FPSLIC uses a code overlay approach to request, load and execute 4 code subroutines stored in the 1M-bit external Flash Memory extending the Program Code space. |
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FPSLIC Baud-Rate Generator
(6 pages, updated 4/01)
The baud-rate generator provides both the receiver and the transmitter with the baud-rate clock, a bit-period clock. |
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FPSLIC On-Chip Partial Reconfiguration of the Embedded AT40K FPGA
(5 pages, updated 1/02)
This Application Note demonstrates the reconfiguration of the FPGA using a built-in cache logic interface. |
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FPSLIC Prototype Kit: Using ATDH40M with Both AT94K and AT40K Devices
(2 pages, updated 7/01)
You can modify the existing ATDH40M Prototype system to work with FPSLIC and the existing AT40K device. |
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Getting Started with ImageCraft C for the FPSLIC Family
(7 pages, updated 11/00)
The purpose of this Application Note is to guide new users through the initial settings of the ImageCraft IDE and compile a simple C program. |
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Getting Started with the IAR Embedded Workbench for FPSLIC
(27 pages, updated 9/04)
With this application note you will learn how to use IAR to design AVR portion of FPSLIC design. |
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High Speed SPI Functional Block for the FPSLIC
(5 pages, updated 7/04)
This application note describes how to implement a high speed Master SPI in the FPSLIC. |
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Implementing a Single-coefficient Multiplier
(5 pages, updated 03/02) |
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Implementing AVR-like I/O Ports on the AT94K FPGA
(7 pages, updated 12/01)
This Application Note explains how the FPGA core of the AT94K FPSLIC device can be used to expand the peripherals of the AVR Core. |
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Implementing FreeRAM inside the FPGA or AT94K Series FPSLIC Using VHDL with IP Core Generator
(11 pages, updated 8/01)
This Application Note explains how to use VHDL with IP Core Generator to implement the FreeRAM inside the AT40K FPGA and the AT94K FPSLIC. |
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Implementing the "Scrolling Design" on the ATSTK94 FPSLIC Starter Kit
(5 pages, updated 6/01)
This Application Note explains how to use the alpha-numeric display connected to the FPGA and the LED driven by PortD from the AVR. |
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Implementing the Test-Bitstream Design on the ATSTK94 FPSLIC Starter Kit
(13 pages, updated 5/01)
The test-bitstream design tests the functionality of the starter kit. |
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IP Core Generator
(5 pages, updated 2/02)
Parameterized IP Core Generator available for the AT40K/AT40KAL series FPGA and AT94K series FPSLIC. |
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IP Core Generator Absolute Value
(3 pages, updated 1/02)
This generator takes an input and generates the absolute value. |
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IP Core Generator Accumulator
(4 pages, updated 1/02)
The Accumulator generators add a given number to the register initial value. |
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IP Core Generator Adders
(6 pages, updated 1/02)
This generator can be used to generate an n-bit Carry Select Adder. |
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IP Core Generator Bus Ripper
(3 pages, updated 1/02)
The Bus Ripper generator allows the user to produce variable-width “soft” buffers for re-naming buses within a design. |
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IP Core Generator Comparator
(4 pages, updated 1/02)
The Comparator Generator created the follwing comparators: Equals, NotEquals, LessThan, LessThanOrEqualTo, GreaterThan and GreaterThanOrEqualTo. |
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IP Core Generator Constant
(3 pages, updated 1/02)
This generator creates a Constant with the specified values. |
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IP Core Generator Decoder
(5 pages, updated 1/02)
The Decoder generator can be used to create a full or partial decode of the specified number of bits of input or output. |
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IP Core Generator I/O Buffer
(8 pages, updated 1/02)
The bi-directional I/O buffer generator can be used to generate a soft macro (schematic only) which uses the specified options. |
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IP Core Generator Multiplier
(12 pages, updated 12/01)
The Multiplier generator can be used to create a signed or unsigned serial by parallel multiplier with serial output. |
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IP Core Generator Shift Register
(5 pages, updated 12/01)
The Shift-register generator can be used to create serial, serial-parallel, parallel-serial and parallel-parallel shift registers. |
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IP Core Macro Generator Counter
(15 pages, updated 1/02)
Generators used to generate Johnson, LFSR, Prescaled, Ripple Carry or Terminal Counters |
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IP Core Macro Generator Deductor
(4 pages, updated 1/02)
The Deductor generator subtracts a given number from the register initial value. |
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IP Core Macro Generator FIFO
(4 pages, updated 1/02)
This generator creates a First-In First-Out (FIFO) buffer that makes use of the RAM cells in the AT40K Series architecture to produce a compact implementation with no read or write latency. |
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IP Core Macro Generator Flip-Flop
(8 pages, updated 1/02)
The D Flip-Flop generator can be used to create a register bank consisting of D-type flip-flops. |
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IP Core Macro Generator Gray Code
(3 pages, updated 1/02)
The Gray Code generator can be used to convert binary code to gray code or gray code to binary code respectively. |
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IP Core Macro Generator Incrementor/Decrementor
(8 pages, updated 1/02)
The Incrementor/Decrementor by 1 generator can be used to add/subtract 1 to/from the current registered value. This generator can be used to create a macro which increments or decrements by 1 a preloaded value or the data input on each rising (or falling) edge of the clock. |
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IP Core Macro Generator Logic Gates
(4 pages, updated 1/02)
A variety of Logic Gates can be generated, each with a programmable number of inverted inputs. |
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IP Core Macro Generator Look-Up Table
(5 pages, updated 1/02)
The Look-Up Table (LUT), or Generic Cell generator can be used as a convenient interface for generating components using the FGENxx and MGENxx generic cell components in the AT40K macro library. The generator allows complete control over
the function of an AT40K core cell, and it allows this function to be replicated n times. |
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IP Core Macro Generator MUX
(4 pages, updated 12/01)
The Mux generator can be used to generate one or more muxes controlled by a single SELECT bus input. |
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IP Core Macro Generator Negate Function
(3 pages, updated 12/01)
The Negate Function generator can be used to create a two’s complement function implemented in a ripple carry manner. |
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IP Core Macro Generator Pulse Generator
(5 pages, updated 12/01)
This can be used to create a pulse generator that asserts its output once every n clock cycles, where n is a fixed value specified by the user. |
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IP Core Macro Generator ROM
(4 pages, updated 12/01)
The ROM generator is used to create synchronous read-only data memories. The data is generated by reading a user-supplied data file and then using the look-up tables within each core cell to store the data. |
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IP Core Macro Generator Subtractor
(6 pages, updated 12/01)
This generator can be used to create an n bit carry-select subtractor. |
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IP Core Macro Generator Transparent Latch
(4 pages, updated 1/02)
The Latch generator can be used to create a D-type transparent latch. |
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Macro Library
(10 pages, updated 12/01)
The Programmable System Level Integrated (PSLI) library of components can be divided into 2 types of macros: functional and dynamic. Functional macros are compo-nents with fixed functionality, such as the 2-input AND gate. Dynamic macros are designed to allow user specification of any desired functionality attached as an attribute, via an equation string, on the symbol. |
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MGL-Based IP Core: Alphanumeric Display Driver
(18 pages, updated 6/02)
This Application Note creates a design that takes the 4-bit input binary number and displays it by lighting the corresponding segments on the alphanumeric display. |
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Mixing C and Assembly Code with IAR Embedded Workbench for FPSLIC
(8 pages, updated 11/00)
This Application Note describes how to use C to control the program flow and main program and assembly modules to control time-critical I/O functions. |
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Motor Control using FPSLIC/FPGA
(8 pages, updated 6/02)
This Application Note describes the implementation of Pulse Width Modulation (PWM) and Quadrature Counter/Decoder Modules using FPGA/FPSLIC for motor control and motor sensor applications. |
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Performing Dynamic Reconfiguration in FPSLIC™ Devices--A Scrolling Message Display
(5 pages, updated 9/04)
This Application Note will provide users information on how to do dynamic reconfiguration on FPSLIC by using an example. |
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Pulse Width Modulation
(9 pages, updated 9/01)
Pulse Width Modulation is a technique to provide a logic "1" and a logic "0" for a period of time. |
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Quadrature Decoder/Counter using Atmel FPGA/FPSLIC
(5 pages, updated 4/02)
This Application Note gives a design example of the Quadrature Decoder/Counter using Atmel FPGA/FPSLIC |
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RC5 IR Remote Control Receiver
(9 pages, updated 5/02)
This Application Note describes a receiver for the frequently used Philips/Sony RC5 coding scheme. |
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Real-Time Clock Using the Asynchronous Timer
(11 pages, updated 5/02)
This Application Note describes how to implement a real-time clock on the FPSLIC embedded microcontroller. |
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Register and Bit Name Definitions for the FPSLIC Family
(2 pages, updated 11/00)
This Application Note contains files which allow the user to use Rgister and Bit names from the databook when writing assembly programs. |
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Setup and Use of the FPSLIC Timers
(16 pages, updated 4/02)
This Application Note describes how to use the different timers of the FPSLIC. The intention of this document is to give a general overview of the timers, show their possibilities and explain how to configure them. The code examples will make this clearer and can be used as guidance for other applications. |
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Setup and Use of the LPM Instructions
(4 pages, updated 4/02)
This Application Note describes how to access the constants saved in the Flash programm memory of the microcontroller embedded in FPSLIC devices. |
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Sleep Modes and Achieving Low-power Supply Current on AT94 Series FPSLIC™ Devices
(13 pages, updated 8/04)
This Application Note is to provide user on different sleep modes and how to achieve low power supply-current on AT94K FPSLIC devices. |
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Software SPI Master
(6 pages, updated 4/02)
This Application Note describes a set of low-level routines for software implementation of the SPI protocol in Master Mode. |
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Stepper Motor Controller
(7 pages, updated 4/02)
This Application Note describes how to implement compact size and high-speed interrupt driver stepper motor controllers. |
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Testing the ATSTK94
(6 pages, updated 3/03)
This tutorial demonstrates how to test the ATSTK94 Starter Kit using a bitstream file. |
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Theory of XY-modem Protocol
(3 pages, updated 1/02)
This Application Note describes the theory of XY-modem protocol used for the "UART and 2-wire Interface reconfiguration of the AT94K FPSLIC using an AT17 Series EEPROM" Application Note. |
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UART and 2-Wire Interface Reconfiguration of the AT94K FPSLIC using an AT17 Series EEPROM
(9 pages, updated 1/02)
This Application Note demonstrates how to reconfigure an AT94K FPSLIC device using its internal UART port, a 2-wire interface port, and an external AT17LV010 EEPROM |
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Using the FPSLIC Hardware Multiplier
(15 pages, updated 01/01)
This Application Note lists program examples for using the Hardware Multiplier. |
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Using the FPSLIC UARTs in C
(7 pages, updated 5/01)
This Application Note describes how to set up and use the UARTs present in most FPSLIC devices. C code examples are included for polled and interrupt controlled UART applications. |
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