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AT40K FPGA Interactive Architecture Guide (updated 04/99)
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Overview
PDF
HDLPlanner® Design Development Environment for HDL-based FPGA Designs (8 pages, updated 10/99)
HDLPlanner solves the addition design cycle problem by providing an environment for creating technology independent HDL designs, which guaranteed to product performance delivering layouts.
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User Guide
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Integrated Development System (8 pages, updated 06/01)
General information of the Atmel FPGA Integrated Development System (IDS).
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