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AVR® 8-Bit RISC - picoPower Active Mode
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Techniques for Low Power Consumption in Active Modes
In theory, digital CMOS logic used in AVR microcontrollers consumes power only when the logical signals or the clock signals are toggling. A signal is toggled when it has a transition from "0" to "1" or a transition from "1" to "0". When all the digital signals are static, like in Power Down mode, only leakage current and current used to enable analog modules is consumed. The power consumption in an MCU can be calculated with the following equation:
P = ½ * F * C * V²
Where F is the toggling frequency, C is the capacitive load and V is the supply voltage.
The toggling frequency for a given device can be seen as the number of gates toggling to achieve a certain task. Power consumption can be reduced by minimizing both the number of gates and the number of times each gate needs to toggle. |
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Clock Gating
Clock gating is used to reduce the toggling frequency. A clock signal can be stopped using a gating element. Any clock distribution or clock domain
that is gated is frozen and won't consume any power. A gating element must handle any spike issue on the clock signal.
The first level of clock gating are traditional sleep modes like Idle, Power- down and Power-save. The sleep modes gate the clock distribution to a group of functionality thereby enabling different levels of sleep and functionality.
The second level of clock gating is the Power Reduction Register (PRR). Many peripheral modules are only used for a short period of time or not at all. The Power Reduction Register contains control bits for disabling unused peripheral modules. The entire clock distribution to disabled peripheral modules is gated. This is more powerful than just disabling the module by its enable bit since the modules IO registers are also disabled by the PRR.
The Power Reduction Register is controlled by software that allows the user to turn on and off peripheral modules at any time. The current state is frozen and all I/O registers are inaccessible when the peripheral module is disabled by the Power Reduction Register. When re-enabled, the peripheral module continues in the same state as before it was disabled. Disabling one peripheral module results in a reduction of 5 to 10% of the total power consumption in active mode and 10 to 20% of the total power consumption in Idle mode.
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Flash Memory Power Consumption and Flash Sampling
Flash memory is an analog block with a static current consumption. Traditional Flash memory designs are always enabled while in active mode. However, at low clock frequencies the Flash read time is less than the clock period so it can be disabled to significantly reduced power consumption. When the clock is running at a few MHz or less, AVR controllers use a technique called "Flash sampling" that enables the Flash for only a few nanoseconds to sample the array's contents and then immediately disables it thereby, reducing average power consumption.
The Flash sampling technique enables a robust, low power Flash design that operates from 1.8 to 5.5V. |
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Pin Leakage and Digital Input Disable Register
AVR microcontrollers mix ADC and digital I/O on the same pins. Using one ADC with a multiplexed input, the microcontroller scans a number of pins. Multiplexing adds flexibility to low pin-count devices but can potentially increase power consumption. A digital input is basically built by two transistors, creating an input buffer. As long as valid high or low voltage levels are applied to the buffer, power consumption is neglectable However, applying voltages in the area of Vcc/2 will create a leakage current through the buffer as both transistors will open slightly.
Since the analog voltage level present at the input adds static power consumption, it is important that the microcontroller be able to disable the digital input. Automatic disabling based on the ADC's multiplexer is not possible since the multiplexer is controlled by the microcontroller's firmware and is not predictable by the microcontroller itself. AVR controllers solve this problem with a Dedicated Input Disable Register, DIDR, with one disable bit per analog input.
The digital input buffers are automatically disabled when sleep mode is entered except for those pins used by the input signal to wake the MCU from a sleep mode. The DIDR contributes to decreased overall power consumption. |
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